Mesa-type PIN diodes are used, for example, in monolithic microwave circuits, attenuators, and other electronic devices requiring excellent high frequency and switching characteristics. A typical mesa-type silicon PIN diode structure is shown in FIG. 1.
In such a structure, a layer of intrinsic material 2 is sandwiched between two layers of opposite conductivity 6, 4. As is known in the art, the top-most layer 6 typically is of P-type conductivity while the bottom layer or substrate layer 4 is of N-type conductivity. The cross-sectional area of the diode 1 taken along the plane of the N-layer 4 decreases from the N-layer 4 to the P-layer 6. Thus, this produces a shape resembling a top-truncated frustrum of a cone or a mesa-like shape. To passivate the junctions, the side-walls of intrinsic layer intrinsic layer 4 typically are coated with a silicon dioxide layer 8A, 8B.
As is well known to those skilled in the art, in such a diode, the intrinsic region 2, has a resistance R.sub.I which, in order to improve the switching characteristics of the device and decrease its power consumption, must be minimized, and which may be computed by using the following equation taken from White, Semiconductor Control, Artech House, 1978, page 64: ##EQU1## wherein, the I-region thickness is given by W.sub.I, charge-carrier mobility is given by u, and the stored charge is denoted by Q.sub.S. Ordinary product design constraints cause W.sub.I to be predetermined, and therefore, effectively the only factor which may be varied to effect the intrinsic region's resistance is the stored charge of the device, Q.sub.S. The stored charge of the device may be expressed as: EQU Qs=It (B)
wherein, I denotes the forward current through the device and t denotes the carrier lifetime in the intrinsic region. By substituting Equation (B) into Equation (A), the resulting equation demonstrates that the carrier lifetime of the device, t, effectively controls its forward resistance, since the current applied to the device may be considered as constant. Therefore, it becomes apparent that the most effective way to minimize the resistance of the intrinsic region 2 is to maximize its carrier lifetime. Accordingly, in order to maximize carrier lifetime through the intrinsic region, the stored charge, Qs, of the device must be made as large as possible.
Unfortunately however, the stored charge of a typical mesa-type PIN diode, like the one shown in FIG. 1, is quite low, on the order of 100 pico-coulombs at a current of 10 milliAmps. Primarily, this is due to two phenomena.
First, the charge stored in the device 1 is reduced through Shockley-Read-Hall (SRH) charge-carrier recombination effects SRH recombination is manifested by the formation of carrier trap levels at or near the the SiO.sub.2 passivation layer of the side-walls 8A, 8B and the doped silicon regions 2, 4, 6 of the device. SRH effects result from the large amount of active surface area exposed to oxidation. Second, when the diode is subjected to periods or conditions of high current density, stored charge is further reduced by Auger charge-carrier scattering effects. Of particular importance to the instant invention, it has been found that large surface area occupied by the P junction 6 atop the mesa (occupying the mesa's entire top surface area) relative to the overall volume of the intrinsic region 4 decreases the amount of charge which may be stored in the intrinsic region 4 of the device 1 through phenomena of either or both of the foregoing effects.